How to pack new U-Boot to FIP.BIN?

Duo
2

Apply my patch which I have used successfully on U-Boot v2024.10-rc2 and v2024.07.

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8e58f641f1..a0eb7dc95e 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -39,6 +39,8 @@ secondary_harts_relocation_error:
 .section .text
 .globl _start
 _start:
+#include <asm/boot0.h>
+_start_real:
 #if CONFIG_IS_ENABLED(RISCV_MMODE)
 	csrr	a0, CSR_MHARTID
 #endif
diff --git a/arch/riscv/include/asm/boot0.h b/arch/riscv/include/asm/boot0.h
new file mode 100644
index 0000000000..d547c19f03
--- /dev/null
+++ b/arch/riscv/include/asm/boot0.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * CVITEK u-boot header
+ */
+
+#ifndef __BOOT0_H__
+#define __BOOT0_H__
+
+/* BOOT0 header information */
+	j boot0_time_recode
+	.balign 4
+	.word 0x33334c42  /* b'BL33' */
+	.word 0xdeadbeea  /* CKSUM */
+	.word 0xdeadbeeb  /* SIZE */
+#ifdef CONFIG_SPL_BUILD
+	.quad	CONFIG_SPL_TEXT_BASE
+#else
+	.quad   CONFIG_TEXT_BASE
+#endif
+	.word 0xdeadbeec
+	.balign 4
+	j boot0_time_recode
+	.balign 4
+/* BOOT0 header end */
+boot0_time_recode:
+	csrr x1, time
+	la x2, BOOT0_START_TIME
+	sw x1, 0(x2)
+	j _start_real
+
+	.global BOOT0_START_TIME
+BOOT0_START_TIME:
+	.word 0
+
+#endif /* __BOOT0_H__ */

It’s not an optimal solution but it does work. One rebuilt, pack the patched u-boot into fip.bin:

--LOADER_2ND='u-boot/u-boot.bin'
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