There are several commits regarding RISC-V and many more on StarFive’s JH7110 SoC:
- add bindings for the PLL clock generator on the JH7110 RISC-V SoC;
- add documentation to describe StarFive System Controller Registers;
- add PLL clock inputs from PLL clock generator;
- add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers;
- modify PLL clocks source to be got from DTS or the fixed factor clocks;
- add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC;
- add PLL clocks input from PLL clocks driver in SYSCRG node;
- add Starfive JH7110 SoC PCIe 2.0 PHY driver support;
- add StarFive JH7110 SoC USB 2.0 PHY dt-binding;
- add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding;
- add Starfive JH7110 SoC USB 2.0 PHY driver support;
- add Starfive JH7110 SoC PCIe 2.0 PHY driver support.